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anonimcs's avatar
anonimcs
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2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
Memory
RichardT_altera's avatar
RichardT_altera
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2 years ago

I think I have found what could be causing the problem.

It might be due to the location assignments in your design, causing it to be over-constrained with placement that's hard to meet timing.


Once I disabled all the location assignments in the assignment editor, the setup timing violation was resolved.

Could you please check and confirm this from your side ?


Regards,

Richard Tan


  • anonimcs's avatar
    anonimcs
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    2 years ago

    By location assignments did you mean the pin assignments ? I cannot change that as that would require a complete new PCB design..