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anonimcs's avatar
anonimcs
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2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
Memory
sstrell's avatar
sstrell
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2 years ago

What exact paths are failing? Usually failures in the core for an EMIF would be due to connections to the user logic, not the IP itself which is usually hardened in the I/O (which target device?).

  • anonimcs's avatar
    anonimcs
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    2 years ago

    Hi,

    The failing paths are included in the screenshot attached here. The target device is an Arria 10