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MHahn4's avatar
MHahn4
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing Constraints for Cyclone 10GX PHY Interlaken

Hi, I'm trying to run the PHY transceivers on a Cyclone 10GX in Interlaken mode. While synthesising, there appears a "Timing requirements not met" critical warning. The problematic paths are for th...
HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
6 years ago

Hi,

Along with derive_pll_clocks, I think to mention create_clock constraint for input reference clock(s) as well.

create_clock -name {pll_refclk0} -period 10  [get_ports {pll_refclk0}]

here, pll_refclk0 is the input clock port in the top module and 10 is 10ns (ie 100MHz input clock).

With Regards,

HPB

  • MHahn4's avatar
    MHahn4
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    I did that already and the two input clocks are detected wth the correct frequency during synthesis.

    That's my full sdc-file:

    create_clock -name {CLK_100MHz} -period 10.000 -waveform { 0.000 5.000 } [get_ports {CLK_100MHz}]
derive_pll_clocks
 
create_clock -name {~ALTERA_CLKUSR~} -period 10.000 -waveform { 0.000 5.000 } { ~ALTERA_CLKUSR~~ibuf|o }