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Altera_Forum
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13 years ago

Throughput Efficiency with half-rate DDR2 controller

I have been developed system which performs simultaneous writing and reading of the same DDR2 RAM (reading from the first half, writing to the second half). Read and write data (32 bit width) are dig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hmm. Thanks, it interesting idea. But let's forget about simultaneous multi-mastering access. Second waveform shows reading procedure by one master only. It looks like DDR controller begins new operation when previous is fully completed only. So, it gives delay 16 cycles in each operation. I don't understand reason of the behavior. I always thought that operations are queued in the controller. PS I try the similar design at system with 32-bit RAM and get same results...

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