Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The issue of Avalon MM templates (read) from DDR2 controller in the EP4SGX230(DE4)

Dear all, I use the burst read master of Avalon MM templates in the Qsys and create the burst read master, clock crossing bridge and DDR2 controller UniPHY. The DDR2 controller UniPHY has 64 bit...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I made a big mistake that the read length is too small (1 byte). And then I increase the read length to 4 bytes, the burst read master can work.

But it's still something wrong. Some read base address can not work after the trigger. Therefore, I supposed the aligned address is the key point.

Does anyone have information about the aligned address of readout from DDR2 in the EP4SGX230(DE4)?

I will appreciate your supports.