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CheepinC_altera's avatar
CheepinC_altera
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3 hours ago
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[Test] Agilex 7 F-Tile PCIe mode supports

Hi,  Can you list down the PCIe modes supported by the Agilex 7 F-Tile?  Thank you.
  • CheepinC_altera's avatar
    1 hour ago

    Hi,


    Here's a summary of the PCIe modes and configurations supported by the Agilex 7 F-Tile:


    Supported PCIe Generations


    F-Tile supports configurations up to PCIe 4.0 x16, with PCIe Gen3 and Gen4 natively supported. Agilex 7 · PCIe



    Supported Interface Modes


    F-Tile supports Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass modes. Agilex 7 · PCIe



    Supported Link Width Configurations


    F-Tile supports up to one Gen4 x16, two Gen4 x8, or four Gen4 x4 PCIe hard IP configurations. Agilex 7 · Transceiver/PHY



    More specifically, the supported configurations are:



    1x PCIe x16 — Root Port or Endpoint (upstream or downstream port) PCIe® Hard IP


    2x PCIe x8 — Endpoint only (various upstream/downstream port combinations) PCIe® Hard IP


    1x PCIe x8 — Root Port or Endpoint PCIe® Hard IP


    4x PCIe x4 — Root Port only (upstream or downstream port) PCIe® Hard IP


    2x PCIe x4 — Root Port or Endpoint PCIe® Hard IP


    1x PCIe x4 — Root Port or Endpoint PCIe® Hard IP




    Port Bifurcation


    The PHY channel assignments per bifurcation mode are:


    1x16: lanes 0–15 on port 0


    2x8: lanes 0–7 on port 0, lanes 8–15 on port 1


    4x4: lanes 0–3 on port 0, lanes 4–7 on port 2, lanes 8–11 on port 1, lanes 12–15 on port 3


    PMA/PCS


    Additional Topology Notes (recent additions)



    A PCIe 1x4 configuration (Topology R) for Root Port mode was introduced in IP v12.1.0, allowing implementation of a PCIe 1x4 Root Port while unused F-Tile FGT channels can be used for Ethernet and other protocols. Agilex 7 · PCIe


    A PCIe 2x8 configuration (Topology S) for Root Port mode was introduced in IP v12.3.0. Agilex 7 · PCIe


    Independent refclk support for 2x4 Hard IP mode is also available, allowing connection to two discrete x4 PCIe endpoints where an independent refclk source is required. Agilex 7 · PCIe




    Hard IP Layers


    Two hard IP modes are supported: Full Hard IP (Transaction Layer, Data Link Layer, and PHY Layer all hardened) and TLP Bypass mode (Transaction Layer Lite + Data Link Layer + PHY Layer). PCIe® Hard IP