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Occasional ContributorTerasic P16E-FMCP PCIE Express 3.0 compatibility issues with AMD processors
Occasional ContributorI believe the sample program was write to/read from on chip memory. It just had a diagnostice message print out comparing the two, and indicating success. I did not choose PIO for system design. So this was the failure point. Every single block of data that was written did not match expected results, ending in failure.
Since I'm just using the Terasic supplied executable, PCIE_FUNDAMENTAL.exe to run the sample program, can you elaborate how I'm supposed to debug and querry the LTSSM state?
ContributorI don't have access to the Terasic application. From your description, the diagnostic tool reports that the PCIe read/write test passes. However, when you perform a manual single-step read/write test on the same design, the readback data does not match the data written.
can you elaborate how I'm supposed to debug and querry the LTSSM state?
>>You can ref doc here https://docs.altera.com/r/docs/683819/26.1/quartus-prime-pro-edition-user-guide/signal-tap-logic-analyzer-introduction
1. Create a Signal Tap (.stp) file.
2. Use the PCIe core clock (coreclkout_hip or equivalent) as the sampling clock.
3. Add the PCIe LTSSM status signal to Signal Tap.
4. Compile the design with Signal Tap enabled.
With the stp, you can also monitor on chip mem read/write/address/data/valid signals to better understand how the application accesses mem and where the data mismatch occurs.
Regards,
Rong
