Forum Discussion
New ContributorTeransceiver & FPGA
Regular ContributorHi,
The Cyclone 10 GX family devices seems to be a good fit they can support upto 12.5 Gbps, enough for SFP or SFP+ interface. You may implement an Ethernet protocol, a light weight Seriallite III or even a custom protocol with 8b/10b or a 64b/66b for your application.
If I were you, decision will consider factors like
1) Whether I need FPGA in my system for other processing as well or rather it is already present so why not use it!
2) If simple data forwarding is required (no processing), then I would go with a simple retimer or PHY device in the path.
Regards
Altera Support
New ContributorHello
Thank you for your response and for your advice.
In fact, the FPGA we are currently using does not have integrated transceivers, and its resources are relatively limited. This is why we are considering a new development to handle both data transmission and additional processing tasks.
Regarding transmission, we plan to exchange both low-speed data and certain logic signals that require very high transmission speeds.
In this context, would it be possible to use two separate transmission channels: one dedicated to low-speed data and the other dedicated to high-speed signals?
Furthermore, for the high-speed signals, can we be assured that they will be properly carried through the entire FPGA chain (TX1 → RX2 → TX2 → RX3 → TX3 → … → TXn → RX1), without data loss or synchronization issues?
If we plan to use Cyclone 10 GX FPGAs, could you provide an estimate of the latency introduced by the transceivers, particularly when using the Native PHY IP for the transmission of high-speed logic signals?
Do you have any other recommendations or points of attention regarding this application?
Thank you in advance for your assistance.
Kind regards,
- Ash_R_Altera
Hi,
"would it be possible to use two separate transmission channels: one dedicated to low-speed data and the other dedicated to high-speed signals?"
Cyclone 10 GX FPGA transceivers supports minimum 1 Gbps data rate and has several channels available for it based on the device you select. If your low-speed requirement is still lower than this, choose the GPIOs, else transceivers. Your pin placement matters here.
"can we be assured that they will be properly carried through the entire FPGA chain"
Altera IP provide a standard interface like AVMM for each of its interface. It is up to the user to provide proper clock domain crossings if any, or connect them directly back to back with each other. If you are able to take care of proper connections, then the data transfers can be assured. I recommend you to do functional verify it with simulations.
"could you provide an estimate of the latency introduced by the transceivers, particularly when using the Native PHY IP"
The latency largely depends upon the data rate and the amount of processing that you want to do in the FPGA. The definite blocks are serializer and deserializer, FIFO between the core logic and the transceiver block. Please refer to the transceiver PHY user guide for ways to enable low latency features of the IP.
https://docs.altera.com/r/docs/683054/current
Regards
