Stratix4GX PCIe development board to used as root port

At this point, I am trying to figure out what verilog modules I can leverage. I understand that I need the time domain translation logic for the speedbridge to work properly.

If I can get the following verilog modules then that can help expedite the development. If there are other major building blocks that can be leveraged then please let me know.

(1) Altera Stratix4GX PCIe PHY - This will be used on both sides for now in reality the emulator side may only pass TLPs and hence may not require PCIe PHY

(2) LCRC Verilog module for Data Link Layer. I understand that Data Link layer needs to pass DLLP packets and that will require additional custom logic.

I am thinking about creating this in a step by step manner.

As a first step I just put a transperent bridge that connects the two PHYs between the root-port BFM and the Altera endpoint.

I have been using the PCIe BFM as root port with Altera PCIe endpoint. I already have Altera PCIe endpoint simulatring with it. If I get the PCIe PHY module then I can connect them back to back. One side will be connected to the BFM and the other side to Altera endpoint. As per my understanding this can be done for Gen1 PCIe.

The next step will be to take the PHY output from each, make it look like TLP