Honored Contributor
Honored ContributorI don’t quite understand your first sentence. You probably meant “[…] so I thought about using the PCIe BFM as root-port and end-point […]”, as we worked out that this setup can not work as a bridge.
So for your task: You need two Gen1 PHYs, right. In between you have to build a bridge, but considering different rates, you have to build something for flow control as you might overrun your non-buffer badly. Remember that both interfaces run at their local clock rates, typically derived from the reception data rate. You will have two simple DLLs on both sides maintaining the respective interface at its specific speed, writing TLPs at reception clock rate to the buffers and maintaining link-local flow control and other DLL tasks accordingly. You will have two uni-directional bridges for the two directions, reading TLPs at sender rate from the receiver’s buffer and outputting them on the sender side, straight through LCRC down to the PHY, whenever there are no other DLLPs to transfer. You will have to have clock domain crossing somewhere around the buffers.
