Stratix4GX PCIe development board to used as root port

I do not have the model for cpu side so initially I am thinking about using the PCIe BFM as root-port and end-point and inbetween them I use this pass through Transparent bridge. First step in doing this will require FPGA PCIe PHY model and synthesizable code. As per my understanding, in PCIe Gen1, I can just use PCIe Gen1 PHY on both side of this transapernt pass through bridge which vall pass all the packets on both sides. I will try to extract it out from already generated IP. Once I have simple pass through bridge working and simulated, I will slowly add components of DLL. I will need LCRC verilog module generator. I also need logic to figure out command boundary. If any of these can be leveraged then that will be great.