Stratix4GX PCIe development board to used as root port

On the side to the Southbridge you will have to have a physical layer and you will have to do DLL stuff according to that link, i.e. flow control and buffering, low-level retransmission and so on. On the other side you have a link of different packet processing speed to the real or simulated CPU. If the model of the CPU includes everything down to DLL, you just have to add a (virtual) DLL on CPU side to your FPGA design with some simple packet exchange between these DLLs. It’s not desirable to simulate the physical layers of both CPU and the transparent FPGA bridge just to burn cycles.