Stratix4GX PCIe development board to used as root port

I don’t know of any official way to get there.

1) You have to setup the Transceivers to do PCIe L1 (Physical Layer) and supply a proper interface (PIPE). It seems one can use the instantiated pcie_serdes component from the top-level PCIe design from MegaWizard.

2) You have to build your own DLL. That’s what PCIe Spec Chapter 3 is all about. That includes:

• Proper handling of L1 at line rate,

• link setup,

• DLLP handling including power saving stuff, TLP acknowledgement, and flow control according to your buffering capabilities,

• proper TLP encapsulation,

• error handling (CRC) and retry mechanism,

• etc.

3) On top of the DLL you can build whatever interface is appropriate for your setup.

4) remember that while you can rate-adapt in this bridge, you have to maintain all timeouts defined by the PCIe spec, otherwise data gets lost on the lowest level, and that’s not what you want.

The following Altera IP functionality should not be in this bridge IP:

1) Configuration space handling,

2) BAR decoding,

3) tag handling,

4) interrupt message generation/decoding,

5) completion timeout,

6) Filtering of unexpected TLPs,

7) etc.

Happy Hacking!