Stratix4GX PCIe development board to used as root port

I don’t know whether I precisely understand your target architecture.

At first, the architecture you specify in your bullets (1), (2) and (3) looks good, but it’s incomplete. What do you want to use the Speedbridge for? It’s an emulation tool and according to the data sheet it works only in conjunction with the proprietary Incisive Palladium simulation system. It is just thought to help you make a simulated CPU with a PCIe root port drive real PCIe hardware. It is not intended to be a PCIe extender or something similar – that’s what PCIe switches are for. That means, wherever you plug the other side of the Speedbridge into – the Palladium –, this computer cannot use the bridge ‘transparently’ at all, I suspect the simulation platform to be optimized for this simulation task and not for physical transparency. But I am not into Speedbridge/Palladium design, so I can be wrong.

So, apart from Speedbridge, let’s say instead of (2) you plug a PCIe FPGA board – maybe a dev kit – into your Custom Mainboard (1). The FPGA is acting as a PCIe root. For argument’s sake, let’s assume that this works physically without mods on the dev kit. Then you put a bridge between your CPU (physical or core) and the AST of the PCIe IP block inside the FPGA. Remember that the PCIe root port is not transparent for your CPU at all, and the bridge will have to maintain all functionality specific to a root complex bridge. That includes and is not limited to CFG space access decoding, Interrupt Message handling from the PCIe leafs, etc.

Again, it is impossible from a PCIe architectural standpoint to have any other PCIe root complex between the CPU and the FPGA root port. With proper OS support it might be possible to have multiple PCIe busses with multiple root complexes side-by-side, but I don’t know precisely if that’s possible at all. I think that whatever you intend should be doable with a standard PCIe architecture, so try to stick with that.