Stratix4GX PCIe development board to used as root port

Thanks for taking the time to explain possible solution to this.

For now if we make the following assumptions:

(1) Custom designed motherboard with a PCIe slot and only pcie south-bridge and no Northbridge is available.

(2) This PCIe slot is used to plug in the FPGA Speedbridge

(3) The other side of the PCIe slot is connected to a PCIe southbridge with all the necessary peripherals to boot.

Based on your explanation, it seems that I can use the FPGA speedbridge device as a Root port - provided that the the CPU behind avalon Streaming interface does not have integrated root port in it.

If yes to the above case then - Can the FPGA speedbridge be completely transparent to the software? From the Avalon Streaming interface back-door when CPU is performing the PCI enumeration, then it is not going to find the FPGA speedbridge as one of the PCI device. As per my understanding, in order to access the config registers inside the FPGA hard IP, one has to use the LMI interface which is not being utilized by the CPU on avalon stream bus. Thus when CPU generates any PCIe config cycles on streaming interface then it will go out in PCIe bus and then to the Southbridge on the motherboard. I can try to run some simulations to get an answer but I thought I ask anyway.

Thanks for your help.