Stratix4GX PCIe development board to used as root port

Reply to# 12: No, in order to emulate a PCIe end point (as layed out by me as option (a)), a speedbridge just has to behave like an end point, and it does so without being a root port. It cannot act as the root port when plugged into a PC. Regarding your final two questions: The FPGA endpoint should pass all transactions generated in your application, sent over AST TX. No, the root port chipset won’t support that kind of another root port configuring the PCIe fabric, this is the task of the processor behind the one and only root complex. In order to be the root port, you have to build a structure like documented in Section 1.3 of the PCIe spec, with your FPGA on top – not as a leaf.

Reply to# 13: If you have a southbridge chip that is connected downstream as an end point to the northbridge over PCIe, then you could use an FPGA in root port mode to drive the southbridge. Problem is: You have to connect to the southbridge over the pins that are currently connected to the northbridge/root complex. As you can’t just unsolder the northbridge and put some wires to your FPGA in its place, you have to build a completely new motherboard around your FPGA and southbridge. Otherwise it’s not possible.

I have to insist: You cannot make your FPGA a root port, connect it to a COTS motherboard’s PCIe slot and expect your CPU inside/behind the FPGA to mutiny and take over the ship, act as the new root. No way. Nada.

These are your options:

• Find an FPGA dev board with a PICMG connector (I don’t know whether that actually exists) and make your FPGA a PCIe root port. Then you can take a PCIe backplane and connect multiple COTS PCIe cards to that backplane and let your CPU/FPGA drive them. I have not seen a backplane yet that has a southbridge on it, as most industrial CPU cards with PICMG have them around the CPU, as most southbridge chips are not connected to the northbridge over official PCIe.

• Use a PCIe southbridge chip. As I don’t think that there are dev kits available with such a setup, you have to build your own board with your application and the southbridge on it.

• Use a COTS northbridge chip. Again, build your own board. Currently there is no chipset that connects to the CPU over PCIe, so you will have to build a different FPGA design that speaks that CPU’s frontside bus language (HyperTransport, QPI, xGTL, etc.).

• Write a PCIe end point and let the CPU on the motherboard handle PCIe configuration, drivers etc.