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SThom66's avatar
SThom66
Icon for New Contributor rankNew Contributor
5 years ago

Stratix V DDR3 simulation not working. All memory signals undefined.

I ran the tcl command to generate the simulation files and then followed the instructions to run the simulation: To generate the VHDL example design, open the Quartus project "generate_sim_example_d...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

Thank you for joining this Intel Community.

May I know which Quartus release and the simulation tools version you are using?

Can you attach your IP top level file that can be opened by the IP parameter editor (or the .qsys file if the IP is instantiated in QSYS)? I’d like to check if the simulation example design works here.

Thanks

Regards,

Aida

  • SimonRichter's avatar
    SimonRichter
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi,

    I have a similar issue with a simulated UniPHY based CycloneV DDR3 controller. I've tracked it down to the the CSR port on the DDR3 block, which isn't reset properly, so its csr_waitrequest, csr_rdata and csr_rdata_valid signals remain undefined.

    The issue seems to be that the component instantiation_name_0002 (with "instantiation_name" replaced by the actual name) contains a signal csr_reset_n_ports_inv that is uninitialized and passed as the reset signal to the mm_interconnect_1 instance contained within it. It's obvious that this is an error, as that name exists only twice in the whole file, once as the signal definition and once where it is connected to an in port.

    Inserting a line

    csr_reset_n_ports_inv <= not csr_reset_n;

    somewhere in the architecture body fixed this.

    If the design connects both the CSR and the AVL ports to the same bus, this will make the entire bus appear as 'U' in simulation.

    Simon