Forum Discussion

User1573261788318367's avatar
User1573261788318367
Icon for New Contributor rankNew Contributor
6 years ago

Stratix 10M PCIe BAR0 size incorrect

Hi, I have a super simple design right now. The Stratix 10M PCIe HIP (generated in qsys) has its rxm_bar0 interface exported, and this IP is instantiated in a top-level wrapper. In Qsys, I've config...
User1573261788318367's avatar
User1573261788318367
Icon for New Contributor rankNew Contributor
6 years ago

BAR1 is disabled.

I figured out that the problem was actually with my memset and msync called, but I can't figure out why they cause bus error. If write to the pointer like u32_ptr[0], u32_ptr[1], etc. then there are no issues, but memset causes bus error.