Contributor
ContributorHi @YuanLi_S_Intel,
Thanks for the response.
Your explanation of the issue matches my understanding of it as I described in my original post, where the problem emanates not from any physical limitation in the clocking architecture, but rather merely a semantic limitation resulting from having a partition boundary that Quartus creates there of its own volition.
I'm intimately familiar with the clock distribution architecture of the Stratix 10, and there were good reasons why I was using a gated clock, and specifically sector clock gating as opposed to root clock gating (reasons I can't get into here as they pertain to proprietary aspects of my broader design). Nevertheless, seeing that a quick resolution to this issue would not be forthcoming, I've modified my design to use a non-gated version of the clock instead for the chip ID interface. An unfortunate workaround.
Still, for future occurrences of similar scenarios where one would like to use sector clock gating with the chip ID interface, other than "don't do that", will there be any resolution coming from Altera/Intel to elimintate this limitation?
It seems to me that the obvious solution would be simply for Quartus to not create a partition boundary there, a partition boundary that doesn't serve any apparent purpose. If it didn't automatically create that partition boundary, this problem wouldn't exist.
-Roee
