Stratix 10 SX Low Latency 40G Ethernet IP
I am attempting to use the Low Latency 40G Ethernet IP in a 1SX280HN2F43I2LPAS chip using Quartus 20.4 Pro. I am unable to get the tx_lanes_stable signal to go high or establish a link through an optical transceiver.
The locked signals from both internal PLLs miss timing to the reset synchronizers by 90+ nanoseconds. The clk_ref is being supplied a 322.265625 MHz clock that is not the correct frequency at power on and is configured through the design. The clk_status and reconfig_clk are bing supplied a 160 MHz clock.
When the clk_ref is set correctly the ATX PLL is recalibrated and then once it achieves lock the csr_rst_n, tx_rst_n, and rx_rst_n resets are asserted for 255 cycles of the 160 MHz clock.
My main questions are why are those paths failing by so much and what can I do to establish a connection?