Stratix 10 Phylite IP , deviation in data sampling at different groups(Input Path Signal)

Hi Ash_R,

In dynamic reconfiguration , though I increase the tap value around mid(262) for pin input , I didn't find any delay in actual simulation .I referred the below one. Here I have doubt that how will we select the dq pin between 2 and 9.Additionally at specific pin selection (from 2 to 9) , what I need to keep at field[8:7]?

Please help me with this