Stratix 10 Mailbox Client IP: max input clock frequency specification

Thanks, @YuanLi_S_Intel. I'll look forward to hearing the outcome of your discussion with your internal team.

Also, in the mean time I've poked around a bit in what Quartus produces with this IP core, which is a wrapper/bridge to the SDM, and I have a hunch as to what's behind all this. I see the following:

It looks as though Quartus creates a bunch of soft interface logic (using general fabric resources) between the user-visible ports of the core and the actual SDM hard block, and this soft interface logic includes an asynchronous clock domain crossing between the user's clock and an internal oscillator clock. And interestingly, that internal oscillator clock is being auto-constrained to 250 MHz. Does that ring true?

So it may be that the SDM hard block proper has a 250 MHz limitation, as you said. But then...

Taking an educated guess here, I suspect that the 250 MHz internal oscillator clock is being used internally in this IP core to satisfy the SDM hard block's clock frequency limitation independently of the user's clock frequency. And that clock domain crossing, if it was implemented properly in the soft interface logic inside this IP core, should relieve the user from having to deal with any such frequency limitation in the user's own clock domain. A reasonable design approach, if that's how this IP core was designed.

So could it be that the 250 MHz limitation is just an internal limitation of the SDM hard block as you've said, but is handled by the soft interface logic and internal oscillator clock inside this IP core, hidden from the user? And as such, is the mention of this limitation in the user guide of this IP core nothing more than a relic that ended up in the wrong place, whereas it doesn't actually pertain to the user clock? Is that the case?

-Roee