Contributor
ContributorHi @YuanLi_S_Intel,
Thank you, but I'm confused by your response. Of course you need to make sure that a design is fully constrained and must close timing properly. You need to do this always, not just if you're targeting a clock frequency above some recommended value. That's a fundamental part of the design implementation process in general, so I'm not sure what distinction you're making above 250 MHz. And also, generally speaking, if you don't close timing properly, a design won't necessarily just "run at slower speed". Rather, with timing violations present, a design cannot be assumed to function correctly in hardware at all. So your comment raises more questions than it answers.
I'll ask my question again, in the form of a specific example:
A customer's design includes the Mailbox Client IP core. The design is fully constrained, and the clock frequency is specified to be 400 MHz. The customer ignored the unexplained 250 MHz max recommendation in question. The design fully meets timing at 400 MHz, as indicated in Quartus timing analysis. Is there any problem at all? Yes or no?
Thanks,
-Roee
