Forum Discussion
YuanLi_S_Intel
Regular Contributor
6 years agoHi William,
This is expected if your S10 Design doesnt contain a remote system update host controller and a Mailbox Client Intel Stratix 10 FPGA IP. Please refer to link below for the design needed to perform RSU.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-config.pdf (Page 122)
Regards,
YL
WGith
Occasional Contributor
6 years agoHI,
I followed the app note and created the following mapping.
BLOCK START ADDRESS END ADDRESS
BOOT_INFO 0x00000000 0x0010FFFF
FACTORY_IMAGE 0x00110000 0x00487FFF (0x00443FFF)
SPT0 0x00488000 0x0048FFFF
SPT1 0x00490000 0x00497FFF
CPB0 0x00498000 0x0049FFFF
CPB1 0x004A0000 0x004A7FFF
P1 0x004A8000 0x007DBFFF
Configuration device: 1SG085HN1AS
Configuration mode: Active Serial x4
Notes:
- Data checksum for this conversion is 0xB3D7AA8A
- All the addresses in this file are byte addresses
I then loaded the flash with my new .jic file and then loaded the design.
I am now able to get status back from usercode 0x5b which points that I loaded the image at 0x004A8000.
I still can’t get user command 0x5C to work no matter what I do.
I am sending the following commands at the moment
Base+0 , 0x5C(command), 0x2 (length)
Base+0, 0x0(command), 0x0(length)
Base+1, 0x004A8000(start address)