Forum Discussion
YuanLi_S_Intel
Regular Contributor
6 years agoHi William,
I have tested the command on v19.1 Pro and it seems like there is no problem in executing it. It seems to me that it might be due to command execution flow issue. I have included the flow to execute the command in TCL using system console:
global omp b0 b1 b2 b3 b4 b5 b6 b7 b8
#writing the command header (Get_IDCODE)
master_write_32 $omp $b1 0x00000010
#Read ISR (Expect to get 0x3)
set ISR [master_read_32 $omp $b8 1]
while {$ISR != 0x00000003} {
puts "ISR is not ready yet!"
set ISR [master_read_32 $omp $b8 1]
}
#Read Response FIFO fill level, EOP and SOP (Expect to get 0x9) (optional)
set SOP_EOP_FIFO [master_read_32 $omp $b6 1]
while {$SOP_EOP_FIFO != 0x00000009} {
puts "SOP_EOP_FIFO is not ready yet!"
set SOP_EOP_FIFO [master_read_32 $omp $b6 1]
}
#read offset 5 for the first packet of data (Expect to get 0x1000)
master_read_32 $omp $b5 1
#Read Response FIFO fill level, EOP and SOP (Expect to get 0x6) (optional)
set SOP_EOP_FIFO [master_read_32 $omp $b6 1]
while {$SOP_EOP_FIFO != 0x00000006} {
puts "SOP_EOP_FIFO is not ready yet!"
set SOP_EOP_FIFO [master_read_32 $omp $b6 1]
}
#read offset 5 again to retrieve the response argument (in this case, this command only has one response argument, which is the IDCODE)
master_read_32 $omp $b5 1
Hope it helps.
Thanks,
YL
WGith
Occasional Contributor
6 years agoHi,
I was able to figure out my problem. I was given AN 891, Using the Reset Release Intel Stratix 10 FPGA IP.
I didn’t change anything in my code except connected up this block to my reset signals and now I see 0x3h as my response in the ISR.
Thank you,
--Will