Stratix 10 fPLL is cascade source mode doesn't lock

Hello.

Let's concentrate on test project that I can share. It can reproduce the issue that I am talking about.

I changed the project (see the one attached to the message). Now it can reconfigure transceiver fPLL (xcvr_tr_fpll) and it use either reference fixed clock or clock from cascade source fPLL (xcvr_cs_fpll).

After power-up, XCVRs and xcvr_tr_fpll are calibrated using fixed reference clock (100MHz). xcvr_cs_fpll is calibrated using clock from RX XCVR but it is not stable, so lock signal is not stable too.

The steps to reconfigure using clock from xcvr_cs_fpll:

1. Set lock to ref. for RX XCVR.
2. Assertiong of reset to TX XCVR.
3. Recalibration of xcvr_cs_fpll
4. Reconfiguration of xcvr_tr_fpll (setting pre-reconfig bit, changing reference clock muxer, changing dividers, etc.)
5. Recalibration of xcvr_tr_fpll.
6. Deassertiong of reset to TX XCVR

If project was compiled with Quartus Pro 21.2, after step 6, lock signals of fPLLs are stable, clock that comes from TX XCVR is equal to expected value (156.25MHz)

If project was compiled with Quartus Pro 23.4 or 25.3 there are no lock on fPLLs outputs and as a consequence no stable clock from TX XCVR.

So, the result depends on Quartus version.

cs_fpll_controller.sv recalibrates xcvr_cs_fpll.

tr_fpll_controller.sv reconfigures and recalibrates xcvr_tr_fpll (the registers used for reconfiguration can be found as localparams).