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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Stratix 10 DDR EMIF pin map implements works for example design but fails for our board design

Hi, We have two DDR4 EMIFs on each die of 1SG10MHN3F74C2LG_U1 FPGA on our boards. The earlier implementation of our board had mistakes and the control address pins were split across banks and also p...
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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Thank you. I was able to implement our design with the revised pin map once I move the reference clocks to a different bank.

Best,

Bharat