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Occasional Contributor

1 year ago

Stratix 10 DDR EMIF pin map implements works for example design but fails for our board design

Hi, We have two DDR4 EMIFs on each die of 1SG10MHN3F74C2LG_U1 FPGA on our boards. The earlier implementation of our board had mistakes and the control address pins were split across banks and also p...

ed_synth_22_3_0_104.qar1.2 MB

ed_synth_qsf.txt56 KB

Memory

sstrell

Super Contributor

1 year ago

I'd bring the design into Interface Planner to verify the legal locations for the adjustments you are making to pin placement.

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Stratix 10 DDR EMIF pin map implements works for example design but fails for our board design

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