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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Stratix 10 DDR EMIF pin map implements works for example design but fails for our board design

Hi, We have two DDR4 EMIFs on each die of 1SG10MHN3F74C2LG_U1 FPGA on our boards. The earlier implementation of our board had mistakes and the control address pins were split across banks and also p...
Memory
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

I'd bring the design into Interface Planner to verify the legal locations for the adjustments you are making to pin placement.