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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Stratix 10 DDR EMIF pin map implements works for example design but fails for our board design

Hi, We have two DDR4 EMIFs on each die of 1SG10MHN3F74C2LG_U1 FPGA on our boards. The earlier implementation of our board had mistakes and the control address pins were split across banks and also p...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi BB,


What is the difference between ddr_u1 and ed_synth?

Is it on different design and device?


How many EMIF IP in your design?


The Quartus version is 22.3, correct?


Regards,

Adzim