Stratix 10 : Critical Warning: DDR Timing requirements not met

Hi Adzim,

You said : " Then the timing closure issue is between the EMIF IP and other design block.". How do you know that?

From what I see, the timing closure issue is between :{memory_ddr4x72_wrapper_a|u0|emif_s10_0|emif_s10_0|ecc_core|core|ecc|internal_master_wr_data[xxx]}

and :{memory_ddr4x72_wrapper_a|u0|emif_s10_0|emif_s10_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[xxx].lane_gen[xxx].lane_inst|lane_inst~phy_reg1}

So between emif_core|ECC|internal_master_wr_data AND emif_core|tile|lane|phy

So not between the core and another design block?

I have added the pipeline asked in the report.

I am relaunching the build.