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Renardo18's avatar
Renardo18
Icon for New Contributor rankNew Contributor
3 years ago

Stratix 10 : Critical Warning: DDR Timing requirements not met

​ I have two DDR4 ('DDR A' and 'DDR B') in my project, and I am using two DDR4 EMIF controller for Stratix 10. My problem is the 2 of them don't meet timing, the compilation report gives this kin...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello Renardo18,


The timing issue has occurred at the core transfer path.

Then the timing closure issue is between the EMIF IP and other design block.

You can remove other IP in the design and just have both EMIF IPs in your design.

Try to compile the design and check if there is any timing violation.

Don't use IOPLL as the reference clock to the EMIF IP.


21st July is about 2 weeks and it's too long.

I need to close it first.

Then you can file another thread for requesting on timing closure recommendation.


Regards,

Adzim