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Renardo18's avatar
Renardo18
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3 years ago

Stratix 10 : Critical Warning: DDR Timing requirements not met

​ I have two DDR4 ('DDR A' and 'DDR B') in my project, and I am using two DDR4 EMIF controller for Stratix 10. My problem is the 2 of them don't meet timing, the compilation report gives this kin...
Renardo18's avatar
Renardo18
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3 years ago

Hi Adzim,

Can you confirm that you have add the pipelines registers and it has solved the timing violations in the DDR controller ? Because I don't see why adding pipeline between a register controller and the 40G ethernet IP would solve timing in the DDR controller?

2 months ago, in a previous message posted on intel community forum, the first thing you told me was to run FAST-FORWARD compilation, and I have added several recommandations and done many design changes to be compliant with the report, and it didn't change anything.

Also please note that I am on vacation until July 21st. Would it be possible not to close this topic until then?

Also please confirm that applying these pipelines on the reset of the 40G ethernet IP will solve timing in the DDR controller (I have serious doubts about it)?

Thanks