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Renardo18's avatar
Renardo18
Icon for New Contributor rankNew Contributor
3 years ago

Stratix 10 : Critical Warning: DDR Timing requirements not met

​ I have two DDR4 ('DDR A' and 'DDR B') in my project, and I am using two DDR4 EMIF controller for Stratix 10. My problem is the 2 of them don't meet timing, the compilation report gives this kin...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


I have checked the design and run the Fast Forward Timing Closure Recommendation.

You have to add pipeline or register to the paths that has been recommended in the report.



Regards,

Adzim