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Renardo18's avatar
Renardo18
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3 years ago

Stratix 10 : Critical Warning: DDR Timing requirements not met

I have two DDR4 ('DDR A' and 'DDR B') in my project, and I am using two DDR4 EMIF controller for Stratix 10. My problem is the 2 of them don't meet timing, the compilation report gives this kind of...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

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Renardo18's avatar
Renardo18
Icon for New Contributor rankNew Contributor
3 years ago

Hi AdzimZM and SyafieqS,

I have tried the following command :

if {![is_post_route]} {
set_min_delay -from [get_keepers "memory_ddr4x72_wrapper_a\|u0\|emif_s10_0\|emif_s10_0\|ecc_core\|core\|ecc\|internal_master_wr_data\[*\]*"] -to {memory_ddr4x72_wrapper_a|u0|emif_s10_0|emif_s10_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[*].lane_gen[*].lane_inst|lane_inst~phy_reg1} 4.114
}

The path with the worst negative slack of my paths had a Data Delay of 3.74. I then added 10% to this value as you told me : 3.74*1.1 = 4.114

The problem is that this made the timing analysis of my design way worse : now I have 500+ of this failing paths in my DDR. (It used to be 30 path only).

Am I doing something wrong?