Stratix 10 : Critical Warning: DDR Timing requirements not met

Hi Adzim,

Thank you for you answer.

Isn't there a missing '}' after the first 'path' of the command you want me to run?

You mention "value is 10% more than the data delay of path", do you mean I need to run this command for each and every failing path?

In my first question, I mentioned that there were 29 failing paths, but today, after I relaunched the build yesterday, I have 75 failing paths in the DDR.. So more than yesterday, and probably some different ones.

Also, I did run fast forward recompile, I obtained these weird results : see the joined files.

1_redblack.png = you can see that the last red path is ddr_b one. The very next one "ddr_a" is black, so meaning it meets timing. Which doesn't reflect what I see in timing analyzer : ddr_a fails timing, and ddr_b does meet timing.

ddra.png and ddrb.png = When I click on each of these paths, it says "meets timing requirements: no further analysis performed".

I am a bit confused here. Do you have a solution?