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Renardo18's avatar
Renardo18
Icon for New Contributor rankNew Contributor
3 years ago

Stratix 10 : Critical Warning: DDR Timing requirements not met

I have two DDR4 ('DDR A' and 'DDR B') in my project, and I am using two DDR4 EMIF controller for Stratix 10. My problem is the 2 of them don't meet timing, the compilation report gives this kind of...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Renardo18,


You can try to set min delay like below:

if { ! [is_post_route]} {

set_min_delay -from [get_keepers {path] -to [path] value

}


value is 10% more than the data delay of the path.


Also can you enable the fast forward recompile feature?

https://www.intel.com/content/www/us/en/docs/programmable/683729/current/fast-forward-compile.html


I'm not sure why the timing violation is occurs in DDRA only.

Maybe you can share the timing report or even the design so that I can check it from my side.


Thanks,

Adzim