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WKapp's avatar
WKapp
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6 years ago

Specifying timing relative to EMIF pll reference clock

Hello all, I am using an Arria 10 10AX027H4F35E3SG and have included a DDR4 EMIF. I am feeding the FPGA a 133MHz clock as the pll reference. This same clock is used for all the board interface tim...
NurAida_A_Intel's avatar
NurAida_A_Intel
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6 years ago

Dear WKapp,

I really thank you for your detail explanation and now I think I understand your issue better. 😊

You are trying to constraint timing for other logic (IN1 and OUT1) and not the EMIF as the EMIF don’t need the additional timing constraint as per I explained before.

And from the diagram you attached, I can see that you are using the afi_clk to drive non-EMIF logic. As far as I know, there are no afi_clk exported from EMIF IP unless you are using “Hard PHY only” mode. Are you using “Hard PHY only” mode?

This afi_clk is actually meant for the custom controller to use and not for other logic like External FF.

Anyway, here is some constraint guideline that I hope is helpful for you to get some idea on how to constraint timing --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf

I believed the problem you are facing now is more to timing issue and not EMIF. My suggestion to you is to open new thread if you encounter any issue from the documentation and Timing expert will help you.

Thanks

Regards,

NAli1

  • WKapp's avatar
    WKapp
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    6 years ago
    NAli1, Yes, I am using Hard PHY only. I know how to write timing constraints. I am not looking for help in how to create the sdc file in detail. What I was hoping to get from this original post was a philosophical answer about how to approach timing in my situation. The design I am working on was a working design but had been in a Stratix II GX part. The memory controller was an ALTMEMPHY. That controller included a PLL but its output clocks were in phase with the PLL reference clock. All the board timing worked out since the board clock was used as the PLL reference clock. The EMIF PLL does not allow me to generate output clocks that are in phase with the PLL reference clock. If I use the PLL reference clock in my timing constraints, there is a huge amount of variation imposed by the fact that the clocks are not in phase, and it becomes difficult if not impossible to meet timing at 133MHz, something that was child’s play for the Stratix II GX. I was hoping you knew something I did not, and there was a trick to help me with timing in this situation. I can’t be the first one that has implemented an EMIF and needs a board clock, too! I am not in a position to put FIFOs in all the interfaces with different clocks as latency for these interfaces is important. Am I missing something? Bill