Specifying timing relative to EMIF pll reference clock

NAli1, I am afraid you do not understand at all. Let me try again. The diagram shows a box labeled Clock Distribution. This box outputs 3 copies of the exact same clock on the board. All are matched lengths and for this analysis you should assume there is 0 skew between them. One clock goes to an external FF that outputs IN1. One clock goes to external FF whose input is OUT1. The last clock goes to the FPGA and is the pll reference clock input for the EMIF. The pll inside the FPGA is part of the EMIF IP, I did not show the rest of the EMIF nor did I show the DDR4 as they are not important to this discussion. As I am sure you are aware, the EMIF pll outputs the clocks that are to be used by all the user logic inside the FPGA. I have shown just one of these clocks, afi_clk. It is used to clock internal FFs that clock in the signal IN1 and also clock out the signal OUT1. In this design, the frequency of the pll input reference clock is the same as afi_clk. As I am sure you are also aware, the phase of afi_clk is not controlled with respect to the input reference clock. This is the crux of the problem. If the pll were capable of operating in “normal” mode, the output clocks would be in phase with the input reference clock. However, since the pll is in “emif” mode, the phase is not controlled. Without any phase relationship, there seems to be no way to write timing constraints for IN1 and OUT1 since the clocks used by the external FFs are not in phase with afi_clk. So, how does one write timing constraints for the FPGA inputs and outputs like IN1 and OUT1? Thanks, Bill