New Contributor
Frequent ContributorHi WKapp,
I am sorry if I misunderstood your question. Perhaps what I replied previously is too general. Let me try to clarify again and be more specific. đ Letâs talk about 2 different perspective as below:
1. EMIF IP perspective:
2. General perspective ( Ex: customer own design and etc)
1. EMIF IP:
Question: What is the recommended way to constrain timing to a board clock that is used as the reference for the EMIF PLL?
Answer: For Arria 10 EMIF, the clock input pin (emif pll ref clk) is connected to dedicated clock pin thus you do not need additional constrain timing.
Question: Would it be safe to manually edit the pll verilog and change the compensation_mode from "emif" to "normal"?
Answer: I assume you are talking about EMIF IP. For EMIF, the compensation mode is already customize for that EMIF IP and it is not changeable. In short, user do not need to worry about what mode they are using because the IP will take care of it.
For more information about the PLL clock you may refer to this emif handbook Ă https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf
2. General perspective ( Ex: customer own design and etc)
I am not sure why you still able to see the âemifâ setting as at my side I am not seeing this listed (see my 2nd screenshot). Even in Arria 10 device handbook chapter 4.2.4. Clock Feedback Modes also didnât support âemifâ mode. Ă https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf
Also another way I would recommend you change the PLL compensation mode is by generating the IOPLL from the Qsys IP with the correct compensation mode selected.
Hope this answered the questions.
Regards,
NAli1
New ContributorNAli1,
I am sorry if I am not stating my question properly, I do not think you understand what I am asking. So, I will try to ask more clearly with the help of a picture.
Question: What is the recommended way to constrain timing to a board clock that is used as the reference for the EMIF PLL?
Answer: For Arria 10 EMIF, the clock input pin (emif pll ref clk) is connected to dedicated clock pin thus you do not need additional constrain timing.
I understand that the memory timing is all constrained, and in my design the memory portion meets timing. My question is not about the memory timing, it is about timing of other FPGA elements. Please look at the following picture (sorry it is rotated):
First of all, the clock distribution on the board guarantees that all the clocks are in phase at their destinations. For the purpose of this analysis, please assume the skew between clocks is 0.
I have shown 1 input to the FPGA and 1 output from the FPGA, both are connected to external FFs. The board clock that connects to the FFs is the same clock used as the PLL reference clock input. The PLL shown inside the FPGA is the one instantiated as part of the EMIF, and one of its output clocks is used inside the FPGA to clock all the fabric.
My problem is that the since the PLL has compenstation_mode = "emif", there is no guaranteed phase relationship between the PLL reference clock input (board clock) and the internal FPGA clock (afi_clk). I want to specify timing constraints for the inputs and outputs relative to the board clock but cannot since there is no known phase relationship.
I originally thought I could change the mode of the PLL manually to "normal". If I could, this would make afi_clk in phase with the PLL reference clock, and I could use the PLL reference clock in my timing constraints. However, I cannot set the mode to "normal". It appears that "emif" mode is similar to "direct" mode in that it does not care about the phase.
I hope the above is clear.
So, please explain, how do I create timing constraints for my example input and output?
Thanks,
Bill
