New Contributor
Frequent ContributorDear WKapp,
EMIF mode has been removed or no longer available from the Assignment Editor list in newer Quartus version ( for example v18.1). Hence, may I know what Quartus version are you using? I suggest you to use the latest version like 18.1.
Below is just for your information about the EMIF mode😊
By default, the clock feedback mode is "direct" compensation mode where PLL does not compensate for any clock networks. To change the mode, you can directly change at the Assignment Editor or your verilog file and re-compile your design.
Hope this helps.
Thanks
Regards,
NAli1
New ContributorNAli1,
Thanks for the reply. Not sure the source of your information, but my IP was generated with Quartus Prime Pro 18.1 and it has selected "emif" as the compensation_mode for the PLL. I also generated the IP with Quartus Prime Pro 19.1 and it, too, selects "emif" for the compensation_mode.
I did try to manually edit the file to select "normal", but this fails in the fitter, unable to place an auto promoted global signal from the PLL.
I would like to ask a more general type question:
When designing an FPGA such as the Arria 10 and included in the design is an EMIF such as mine, the PLL outputs the clocks that should be used for all the FPGA logic inside. Now, these PLL output clocks are not phase related to the PLL input reference clock. So, what are the best practices for interfacing the FPGA to other board elements?
In my case, I have a board clock that is used by essentially everything on the board. In a previous FPGA (a GX130), its memory controller (an ALTMEMPHY) included a PLL that operated in "normal" mode, so its output clocks were in phase with the input reference clock, and I fed that from the board clock. Now, with the Arria 10, all the interfaces that use the board clock can never be used with the FPGA io since that clock is not in phase with the FPGA fabric.
Thanks,
Bill
