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Altera_Forum's avatar
Altera_Forum
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10 years ago

Some questions in FIFO IPcore, I use the EP4CE55F23I7

HI i have some question...In my project, I use fifo ipcore, when I use the depth of 8192,4096 or 2048, the data I read is correct, but after increasing the depth, such as 32768,65536 or bigger, the data read out is wrong, it is almost wrong. I use signaltap ii analysis, data is right to write , but not to read.....10bit fifo. and FPGA is Cyclone IV EP4CE55F23I7.....waiting for your reply. thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Thanks for your reply.....I solved the problem by using the logiclock to lock the fifo memory. Thanks a lot