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Altera_Forum's avatar
Altera_Forum
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12 years ago

Soft ip core design

Hi, Basically i want to design one fifo soft ip core which should work any vendor FPGA.(I know so many fifo ip core's are there in market:-P). Already i designed fifo(256x8) using VHDL code and sa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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FWIW: Contrary to a statement in that document, if you do concurrent read and write to the same location with the same clock but without 'old data' configured you can get a mixture of the old and new values - you aren't guaranteed to see one or the other.

(OK - that was actually two clock mode with both clocks being the same...)

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I'm afraid we are getting diverted from the original post. Basically I need someone to explain me the steps/process/tools involved in designing a IP core and how different it is from a RTL design. Can I get a reference design for the same?

Thanks in advance,

Karthi. S