Slow PCIe cycles

I have measured RC read -> Endpoint internal memory,

Endpoint read -> RC ( system ) memory

RC read -> Endpoint Configuration register.

All show long latencies and the last one is a reference since the Configuration register is a local register and no fabric or endpoint memory read is involved.

Depending on the PCIe core clock , I'm thinking the turn around number of clocks at the Endpoint may be 40 clocks .

So what we have in the case of the Configuration register reads … is say 483 nS and the PCIe core is running at 100 Mhz so that translates to approx.. 483/10 = 48 approx. clocks. I measure this from when the Configuration Read is seen on the downstream link X1, Gen1, to when the Read Completion is first seen on the upsteam link.

Now for my problem, I figured it was time to run this in ModelSim but have not been successful.

1. I get errors when in QSYS Generate if I select "Testbench Simulation Model " = Verilog per the PCIe user guide example.. ( with none .. Generate runs error free.)

2. I am able to run Modelsim after do msim_setup.tcl , ld_debug , run 140000 ns , however the simulation runs immediately in apparently immediately.

I guess the environment is set up but an actual test_bench is missing that would go through training , config reads, memory read/ writes ... I was thinking such an

example would exist ..

Any ideas on 1 or 2 ?

Thanks, Bob.