Slow DDR2 reading

Might be worth tring to find out if the memory controller is buffering writes in order to do a burst write to the DDR memory, but always doing an actual read transfer.

Some simple timing calculations I did with the SDRAM interface implied it initially latched a write request, then moved it into a burst sized 'write assembly buffer' before finally writing out the accumulated burst.

(It would definitely accept 3 random writes without additional waits.)

Read requests, of course, cannot be latched the same way! But could be quickly responded to from a single 'burst read' buffer.

I was only interested in the timing for random reads and writes.