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Minh_Le's avatar
Minh_Le
Icon for New Contributor rankNew Contributor
3 years ago

Simulation unbound warning

Hi, I'm working on simulation with IP cores and having issue with unbound components. Specifically, the Questa compiler complains about the dcfifo mixed width have declared and instantiated interfa...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Which ip core you're using?

which language you're using for ip generation?

Quartus 18.1 lite or standard or pro?

Have you try simulation with mentor msim_setup.tcl before?


Regards,

Sheng


  • Minh_Le's avatar
    Minh_Le
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Sheng,

    Thanks for reaching out. From the qsys file, <module name="fifo_0" kind="fifo" version="16.1" enabled="1" autoexport="1">, <parameter name="hdlLanguage" value="VERILOG">. It wraps around dcfifo, which instantiate dcfifo_mixed_width. I notice the fifo version is 16.1 and the Quartus Prime version is 18.1.0

    From the Help menu of the GUI : Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition

    We use qsys-generate to regenerate the core files from qsys files, which are checked in to git repo, then use msim_setup.tcl to generate simulation libraries for the cores.

    Thanks,

    -Minh