simulation problem of fft generated from megawizard function

Hello,

I need ip block of FFT in my project which has to be integrated with other blocks and used in SOPC builder tool of QUARTUS II.I am generating FFT megafunction using MegaWizard Plug-In Manager.The fft.vhd file am using in ModelSim for simulation showing ** Warning: (vsim-3473) Component instance "auk_dspip_r22sdf_top_fft_110_inst : auk_dspip_r22sdf_top_fft_110" is not bound. The code i am using is given below

library IEEE;

use IEEE.std_logic_1164.all;

library auk_dspip_r22sdf_lib;

ENTITY fft IS

PORT (

clk : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

fftpts_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0);

inverse : IN STD_LOGIC;

sink_valid : IN STD_LOGIC;

sink_sop : IN STD_LOGIC;

sink_eop : IN STD_LOGIC;

sink_real : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

sink_imag : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

source_ready : IN STD_LOGIC;

fftpts_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);

sink_ready : OUT STD_LOGIC;

source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);

source_sop : OUT STD_LOGIC;

source_eop : OUT STD_LOGIC;

source_valid : OUT STD_LOGIC;

source_real : OUT STD_LOGIC_VECTOR (24 DOWNTO 0);

source_imag : OUT STD_LOGIC_VECTOR (24 DOWNTO 0)

);

END fft;

ARCHITECTURE SYN OF fft IS

COMPONENT auk_dspip_r22sdf_top_fft_110

GENERIC (

MAX_FFTPTS_g : NATURAL;

NUM_STAGES_g : NATURAL;

DATAWIDTH_g : NATURAL;

TWIDWIDTH_g : NATURAL;

MAX_GROW_g : NATURAL;

TWIDROM_BASE_g : STRING;

DSP_ROUNDING_g : NATURAL;

INPUT_FORMAT_g : STRING;

OUTPUT_FORMAT_g : STRING;

REPRESENTATION_g : STRING;

DSP_ARCH_g : NATURAL;

PRUNE_g : STRING

);

PORT (

clk : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

fftpts_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0);

inverse : IN STD_LOGIC;

sink_valid : IN STD_LOGIC;

sink_sop : IN STD_LOGIC;

sink_eop : IN STD_LOGIC;

sink_real : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

sink_imag : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

source_ready : IN STD_LOGIC;

fftpts_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);

sink_ready : OUT STD_LOGIC;

source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);

source_sop : OUT STD_LOGIC;

source_eop : OUT STD_LOGIC;

source_valid : OUT STD_LOGIC;

source_real : OUT STD_LOGIC_VECTOR (24 DOWNTO 0);

source_imag : OUT STD_LOGIC_VECTOR (24 DOWNTO 0)

);

END COMPONENT;

BEGIN

auk_dspip_r22sdf_top_fft_110_inst : auk_dspip_r22sdf_top_fft_110

GENERIC MAP (

MAX_FFTPTS_g => 256,

NUM_STAGES_g => 4,

DATAWIDTH_g => 16,

TWIDWIDTH_g => 16,

MAX_GROW_g => 9,

TWIDROM_BASE_g => "fft_",

DSP_ROUNDING_g => 0,

INPUT_FORMAT_g => "NATURAL_ORDER",

OUTPUT_FORMAT_g => "BIT_REVERSED",

REPRESENTATION_g => "FIXEDPT",

DSP_ARCH_g => 0,

PRUNE_g => "0,0,0,0"

)

PORT MAP (

clk => clk,

reset_n => reset_n,

fftpts_in => fftpts_in,

fftpts_out => fftpts_out,

inverse => inverse,

sink_valid => sink_valid,

sink_sop => sink_sop,

sink_eop => sink_eop,

sink_real => sink_real,

sink_imag => sink_imag,

sink_ready => sink_ready,

sink_error => sink_error,

source_error => source_error,

source_ready => source_ready,

source_sop => source_sop,

source_eop => source_eop,

source_valid => source_valid,

source_real => source_real,

source_imag => source_imag

);

END SYN;

So kindly tell me why this problem is ocurring, i m stuck.Hoping for a quick response.