Simulating the I2C Controller

Definately doable in Modelsim. It can run Testbed scripts, which is where you bring in the entity that needs testing - then simulate whatever response the I2C would give.

library IEEE; 
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all;
entity device_testbench is
end;
architecture test of device_testbench is
 component device is
	PORT (
		CLOCK_50			: IN 		STD_LOGIC;			-- 50 MHz
		KEY				: IN		STD_LOGIC_VECTOR(3 downto 0);
		SW 				: IN 		STD_LOGIC_VECTOR(17 downto 0);
		LEDG				: OUT 	STD_LOGIC_VECTOR(7 downto 0);
		LEDR				: OUT 	STD_LOGIC_VECTOR(17 downto 0);
		LCD_RS, LCD_EN	: OUT		STD_LOGIC;
		LCD_RW			: OUT		STD_LOGIC;
		LCD_ON			: OUT		STD_LOGIC;
		LCD_DATA			: INOUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
		ENET0_RST_N		: OUT		STD_LOGIC;
		ENET0_MDC		: OUT		STD_LOGIC;
		ENET0_MDIO 		: INOUT	STD_LOGIC;
		ENET0_RX_CLK	: IN		STD_LOGIC;
		ENET0_RX_DV		: IN		STD_LOGIC;
		ENET0_RX_ER		: IN		STD_LOGIC;
		ENET0_RX_CRS	: IN		STD_LOGIC;
		ENET0_RX_COL	: IN		STD_LOGIC;
		ENET0_RX_DATA	: IN		STD_LOGIC_VECTOR(3 DOWNTO 0);
		ENET0_INT_N		: IN		STD_LOGIC		
    );
 end component;
  SIGNAL CLOCK_50			: STD_LOGIC;			-- 50 MHz
  SIGNAL KEY				: STD_LOGIC_VECTOR(3 downto 0);
  SIGNAL SW 				: STD_LOGIC_VECTOR(17 downto 0);
  SIGNAL LEDG				: STD_LOGIC_VECTOR(7 downto 0);
  SIGNAL LEDR				: STD_LOGIC_VECTOR(17 downto 0);
  SIGNAL LCD_RS, LCD_EN	: STD_LOGIC;
  SIGNAL LCD_RW			: STD_LOGIC;
  SIGNAL LCD_ON			: STD_LOGIC;
  SIGNAL LCD_DATA			: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL ENET0_RST_N		: STD_LOGIC;
  SIGNAL ENET0_MDC		: STD_LOGIC;
  SIGNAL ENET0_MDIO 		: STD_LOGIC;
  SIGNAL ENET0_RX_CLK	: STD_LOGIC;
  SIGNAL ENET0_RX_DV		: STD_LOGIC;
  SIGNAL ENET0_RX_ER		: STD_LOGIC;
  SIGNAL ENET0_RX_CRS	: STD_LOGIC;
  SIGNAL ENET0_RX_COL	: STD_LOGIC;
  SIGNAL ENET0_RX_DATA	: STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL ENET0_INT_N		: STD_LOGIC;
begin
  -- instantiate device to be tested
  device0: 	device 	port map(CLOCK_50, KEY, SW, LEDG, LEDR, LCD_RS, LCD_EN, LCD_RW, LCD_ON, LCD_DATA, 
											ENET0_RST_N, ENET0_MDC, ENET0_MDIO, ENET0_RX_CLK, ENET0_RX_DV, ENET0_RX_ER, ENET0_RX_CRS, ENET0_RX_COL, ENET0_RX_DATA, ENET0_INT_N);
  -- Generate 50 MHz clock, 20 ns cycle
  process begin
    CLOCK_50 <= '1';
    wait for 10 ns; 
    CLOCK_50 <= '0';
    wait for 10 ns;
  end process;
  -- Operate switch
  process begin
    sw(17) <= '1';
    wait for 100 ns;
    sw(17) <= '0';
    wait;
  end process;
  
  -- MDIO Output from PHY chip
  process begin
    ENET0_MDIO <= 'Z';
    wait for 38527 ns; -- This is where we simulate response from the PHY
    report ("Faking PHY response");
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '1';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '1';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '1';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '1';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '0';
    wait for 400 ns;
    ENET0_MDIO <= '1';
    wait for 400 ns;
    ENET0_MDIO <= 'Z';
    report ("Done faking PHY response");
    wait;
  end process;
  
end;