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Altera_Forum
Honored Contributor
14 years agohello sir, and thanks for your quick response.
Yes I am trying to use the microphone to speak into the de2 board. so i need to create a controller(Master) in VHDL to control the slave(wm8731). Accordings the latter's data sheet, using a two wire transfer i need to send 3 bytes of codes, starting by: a start condition --> address of the slave --> ack(from the slave) --> register address --> ack (from the slave)--> data control--> ack(from the slave)-->stop condition. To do this i developed and FSM, that is going generates the proper clk and data signals. --> it specifies the start and stop conditions --> i created to counters to keep track of teh number of bits and bytes sent, and another one to divide the clk. --> to meet the timing requirements I divided cetain states to 2/3 states. --> since the sdin is bidirectional and open drain, to output logic one on the line it needs to be set to high impedence as follows sdin <= ‘z’ when sdin01 =’1’ else ‘0’ I think my code is okay, but i don't know how to simulate the acknowledgement from the slave. Should you be familiar with this protocol, please kindly advice me. Best Regards.