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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Florian,

Arria V both nativelink and setup script methods (do file .../testbench/mentor/test.do) can be simulated for RS232 UART using VHDL. Check the sample file attached below. I further try out with Arria II, Cyclone V and Stratix V all can work properly.

Ya. UART {RS-232 Serial Port) Intel FPGA IP only supports memory mapped. IRDA UART under university program got the same problem with VHDL language on Arria 10 as well.

Thanks,

Best Regards,

Sheng

  • FHint's avatar
    FHint
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi Sheng,

    I don't understand how you were able to simulate the attached files. When I run the mentor/test.do script with modelsim following warning message appears:

    # ** Warning: (vsim-3473) Component instance "rs232_0 : unsaved_rs232_0" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /unsaved_tb/unsaved_inst File: <path>/test/unsaved/testbench/unsaved.vhd

    Also there is no file regarding the rs232 in the unsaved_tb/simulation/submodules folder:

    This seems to be the same behaviour that I have seen on my computer when trying to simulate with the device set to Arria V.

    Best Regards
    Florian