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Altera_Forum
Honored Contributor
Honored ContributorSGDMA write_waitrequest always 'high'
Hello everyone, In order to achieve my project, I have to use my Nios II in order to send data from my FPGA to a server. My FPGA will have to read data from a Dual port Onchip memory which is c...
Altera_ForumHonored Contributor
Honored ContributorI've been doing a lot of testing but recently a new problem appeared.
It seems that sometimes my full project is corrupted or something like that after a new compilation. I'm using the Simple Socket Server with my design which was working pretty well. But since I try to get data back into the Nios II, my design stay locked after the: Create "simple socket server" task (Prio: 4) Everything's working untill the select(max_socket, &readfs, NULL, NULL, NULL); I guess that I can't receive data anymore but all I did was linking different wire together (in order to send data to the SGDMA) without changing anything about the TSE or the Qsys. I'm trying to compile the project again but it's not the first time I have that problem and it's being quite annoying to compile everything twice or more... Does anyone ever had that problem before? Thanks
